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FEATURES Four 14-Bit DACs in One Package AD7834--Serial Loading AD7835--Parallel 8-/14-Bit Loading Voltage Outputs Power-On Reset Function Max/Min Output Voltage Range of +/-8.192 V Maximum Output Voltage Span of 14 V Common Voltage Reference Inputs User Assigned Device Addressing Clear Function to User-Defined Voltage Surface Mount Packages AD7834--28-Pin SO, DIP and Cerdip AD7835--44-Pin PQFP and PLCC APPLICATIONS Process Control Automatic Test Equipment General Purpose Instrumentation
LC2MOS Quad 14-Bit DAC AD7834/AD7835
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one monolithic chip. The AD7834 and AD7835 have output voltages in the range of 8.192 V with a maximum span of 14 V. The AD7834 is a serial input device. Data is loaded in 16-bit format from the external serial bus, MSB first after two leading 0s, into one of the input latches via DIN, SCLK and FSYNC. The AD7834 has five dedicated package address pins, PA0- PA4, that can be wired to AGND or VCC to permit up to 32 AD7834s to be individually addressed in a multipackage application. The AD7835 can accept either 14-bit parallel loading or double-byte loading, where right-justified data is loaded in one 8-bit and one 6-bit byte. Data is loaded from the external bus into one of the input latches under the control of the WR, CS, BYSHF and DAC channel address pins, A0-A2. With either device, the LDAC signal can be used to update either all four DAC outputs simultaneously or individually, on reception of new data. In addition, for either device, the asynchronous CLR input can be used to set all signal outputs, VOUT1-VOUT4, to the user-defined voltage level on the Device Sense Ground pin, DSG. On power-on, before the power supplies have stabilized, internal circuitry holds the DAC output voltage levels to within 2 V of the DSG potential. As the supplies stabilize, the DAC output levels move to the exact DSG potential (assuming CLR is exercised). The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP packages, and the AD7835 is available in a 44-pin PQFP package and a 44-pin PLCC package.
AD7834 FUNCTIONAL BLOCK DIAGRAM
VCC VDD VSS
DAC 1 LATCH
AD7835 FUNCTIONAL BLOCK DIAGRAM
VCC VDD VSS VREF(-)A VREF(+)A DSG A
VREF(-) VREF(+)
AD7834
PAEN PA0 PA1 PA2 PA3 PA4 FSYNC DIN SCLK AGND
SERIAL-TOPARALLEL CONVERTER CONTROL LOGIC & ADDRESS DECODE
INPUT REGISTER 1
DAC 1 X1
AD7835
VOUT 1
BYSHF DB13
INPUT BUFFER 14
INPUT REGISTER 1
DAC 1 LATCH
DAC 1 X1
VOUT 1
INPUT REGISTER 2
DAC 2 LATCH
DAC 2 X1
DB0
VOUT 2
INPUT REGISTER 2
DAC 2 LATCH
DAC 2 X1
WR CS
INPUT REGISTER 3 DAC 3 LATCH
VOUT 2
INPUT REGISTER 3
DAC 3 LATCH
DAC 3 X1
DAC 3 X1
VOUT 3
VOUT 3
A0 A1
ADDRESS DECODE INPUT REGISTER 4 DAC 4 LATCH DAC 4 X1
INPUT REGISTER 4
DAC 4 LATCH
DAC 4 X1
VOUT 4 CLR
A2
VOUT 4 CLR
DGND
LDAC
DSG
AGND
DGND
LDAC VREF(-)B VREF(+)B DSG B
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7834/AD7835-SPECIFICATIONS DGND = 0 V; T
Parameter
ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error TMIN to TMAX Zero-Scale Error Gain Error Gain Temperature Coefficient2 DC Crosstalk2 REFERENCE INPUTS DC Input Resistance Input Current VREF(+) Range VREF(-) Range [VREF(+)-VREF(-)] DEVICE SENSE GROUND INPUTS Input Current DIGITAL INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance POWER REQUIREMENTS VCC VDD VSS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS ICC IDD ISS A 14 2 0.9 5 4 0.5 4 20 50 30 1 0/+8.192 -8.192/0 5/14 B 14 1 0.9 5 4 0.5 4 20 50 30 1 +7/+8.192 -8.192/0 7/14 S 14 2 0.9 8 5 0.5 4 20 50 30 1 0/+8.192 -8.192/0 5/14 Units Bits LSB max LSB max
(VCC = +5 V 5%; VDD = +15 V 5%; VSS = -15 V 5%; AGND = 1 A = TMIN to TMAX, unless otherwise noted)
Test Conditions/Comments
Guaranteed Monotonic Over Temperature VREF(+) = +7 V, VREF(-) = -7 V
mV max mV max VREF(+) = +7 V, VREF(-) = -7 V mV typ VREF(+) = +7 V, VREF(-) = -7 V ppm FSR/C typ ppm FSR/C max V max See Terminology. RL = 10 k M typ A max V min/max V min/max V min/max
Per Input
For Specified Performance. Can Go as Low as 0 V, but Performance Not Guaranteed Per Input. VDSG = -2 V to +2 V
2 2.4 0.8 10 10 5.0 15.0 -15.0 110 100 0.2 3 6 10 15 10
2 2.4 0.8 10 10 5.0 15.0 -15.0 110 100 0.2 3 6 10 15 10
2 2.4 0.8 10 10 5.0 15.0 -15.0 110 100 0.5 3 6 15 15 15
A max V min V max A max pF max V nom V nom V nom dB typ dB typ mA max mA max mA max mA max mA max mA max
5% for Specified Performance 5% for Specified Performance 5% for Specified Performance
VINH = VCC, VINL = DGND AD7834. VINH = 2.4 V min, VINL = 0.8 V max AD7835. VINH = 2.4 V min, VINL = 0.8 V max AD7834. Outputs Unloaded AD7835. Outputs Unloaded Outputs Unloaded
AC PERFORMANCE CHARACTERISTICS
Parameter
DYNAMIC PERFORMANCE Output Voltage Settling Time Digital-to-Analog Glitch Impulse DC Output Impedance Channel-to-Channel Isolation DAC to DAC Crosstalk Digital Crosstalk Digital Feedthrough - AD7834 Digital Feedthrough - AD7834 Output Noise Spectral Density @ 1 kHz A 10 120 0.5 100 25 3 0.2 0.1 40 B 10 120 0.5 100 25 3 0.2 0.1 40 S
(These characteristics are included for Design Guidance and are not subject to production testing. )
Units s typ nV-s typ typ dB typ nV-s typ nV-s typ nV-s typ nV-s typ nV/Hz typ Test Conditions/Comments Full-Scale Change to 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Measured with VREF(+) = VREF(-) = 0 V. DAC Latch Alternately Loaded with All 0s and All 1s See Terminology See Terminology; Applies to the AD7835 Only See Terminology Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Effect of Input Bus Activity on DAC Output Under Test
10 120 0.5 100 25 3 0.2 0.1 40
All 1s Loaded to DAC. V REF(+) = VREF(-) = 0 V
NOTES 1 Temperature range is as follows: A Version: -40C to +85C; B Version: -40C to +85C; S Version: -55C to +125C. 2 Guaranteed by design. Specifications subject to change without notice
-2-
REV. A
AD7834/AD7835 TIMING SPECIFICATIONS1 (V
Parameter AD7834 Specific t1 2 t2 2 t3 2 t4 t5 t6 t7 t8 t9 t21 AD7835 Specific t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 General t10 100 50 60 66 30 30 40 30 10 0 40 20 15 15 0 0 40 40 10 0 0 0 40
CC
= +5 V 5%; VDD = +15 V 5%; VSS = -15 V 5%; AGND = DGND = 0 V)
Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description SCLK Cycle Time SCLK Low Time @ +25C SCLK Low Time -40C to +85C SCLK Low Time -55C to +125C SCLK High Time FSYNC, PAEN Setup Time FSYNC, PAEN Hold Time Data Setup Time Data Hold Time LDAC to FSYNC Setup Time LDAC to FSYNC Hold Time Delay Between Write Operations A0, A1, A2, BYSHF to CS Setup Time A0, A1, A2, BYSHF to CS Hold Time CS to WR Setup Time CS to WR Hold Time WR Pulse Width Data Setup Time Data Hold Time LDAC to CS Setup Time CS to LDAC Setup Time LDAC to CS Hold Time LDAC, CLR Pulse Width
Limit at TMIN, TMAX
NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice.
A0. A1 A2 BYSHF
t 11
1ST CLK SCLK 2ND CLK
t 12 t 13
t1
24TH CLK
CS
t4
FSYNC
t2
t3
t5
WR
t 15
t 14
t6 t7
DIN LDAC (SIMULTANEOUS UPDATE) LDAC (PRE-CHANNEL UPDATE) D0 D1 D22 D23
t 20
DATA
t 16
t 17
t 10 t8
LDAC (SIMULTANEOUS UPDATE)
t 10
t9
LDAC (PRE-CHANNEL UPDATE)
t 18
t 19
Figure 1. AD7834 Timing Diagram
Figure 2. AD7835 Timing Diagram
REV. A
-3-
AD7834/AD7835
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VCC to DGND . . . . . . . . . . . . . . . -0.3 V, +7 V or VDD + 0.3 V (Whichever Is Lower) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +0.3 V Digital Inputs to DGND . . . . . . . . . . . . . . -0.3 V, VCC + 0.3 V VREF(+) to VREF(-) . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +18 V VREF(+) to AGND . . . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V VREF(-) to AGND . . . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V DSG to AGND . . . . . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V VOUT (1-4) to AGND . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (S Version). . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Plastic Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +75C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260C Cerdip Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +52C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300C
SOIC Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +75C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C PQFP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C PLCC Package JA Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . +55C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C Power Dissipation (Any Package) . . . . . . . . . . . . . . . . 480 mW
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7834/AD7835 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD7834AR AD7834BR AD7834AN AD7834BN AD7834SQ AD7835AS2 AD7835BS2 AD7835AP2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C
Linearity Error (LSBs) 2 1 2 1 2 2 1 2
DNL (LSBs) 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9
Package Option1 R-28 R-28 N-28 N-28 Q-28 S-44 S-44 P-44A
NOTES 1 R = Small Outline IC (SOIC); N = Plastic DIP; Q = Cerdip; S = Plastic Quad Flatpack (PQFP); P = Plastic Leaded Chip Carrier (PLCC). 2 Contact Sales Office for availability.
-4-
REV. A
AD7834/AD7835
AD7834 PIN DESCRIPTION Pin Mnemonic Description
VCC VSS VDD DGND AGND VREF(+) VREF(-) VOUT1 . . . VOUT4 DSG DIN SCLK FSYNC
Logic Power Supply; +5 V 5%. Negative Analog Power Supply; -15 V 5%. Positive Analog Power Supply; +15 V 5%. Digital Ground. Analog Ground. Positive Reference Input. The positive reference voltage is referred to AGND. Negative Reference Input. The negative reference voltage is referred to AGND. DAC Outputs. Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, the DAC outputs are forced to the potential on the DSG pin. Serial Data Input. Clock input for writing data to the device. Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input register are transferred on the rising edge of this signal. Package Address Inputs. These inputs are hardwired high (VCC) or low (DGND) to assign dedicated package addresses in a multipackage environment. Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the device ignores the package address (but not the channel address) in the serial data stream and loads the serial data into the input registers. This feature is useful in a multipackage application where it can be used to load the same data into the same channel in each package. Load DAC Input (level sensitive). This input signal in conjunction with the FSYNC input signal, determines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the device's input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs. Alternatively, if LDAC is kept low while new data is shifted into the device, then the addressed DAC latch (and corresponding analog output) is updated immediately on the rising edge of FSYNC.
PA0 . . . PA4 PAEN
LDAC
CLR
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored and the signal outputs remain switched to the potential on the DSG pin.
PIN CONFIGURATION DIP AND SOIC
VSS 1 DSG 2 VREF(-) 3 VREF(+) 4 NC 5 VOUT2 6 28 AGND 27 NC 26 NC 25 NC
AD7834
24 NC
TOP VIEW 23 VDD VOUT4 7 (Not to Scale) 22 VOUT1 DGND 8 VCC 9 SCLK 10 DIN 11 PA0 12 PA1 13 PA2 14 21 VOUT3 20 CLR 19 LDAC 18 FSYNC 17 PAEN 16 PA4 15 PA3
NC = NO CONNECT
REV. A
-5-
AD7834/AD7835
AD7835 PIN DESCRIPTION
Pin Mnemonic VCC VSS VDD DGND AGND VREF(+)A, VREF(-)A VREF(+)B, VREF(-)B VOUT1 . . . VOUT4 CS DB0 . . . DB13
Description Logic Power Supply; +5 V 5%. Negative Analog Power Supply; -15 V 5%. Positive Analog Power Supply; +15 V 5%. Digital Ground. Analog Ground. Reference Inputs for DACs 1 and 2. These reference voltages are referred to AGND. Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND. DAC Outputs. Level-Triggered Chip Select Input (active low). The device is selected when this input is low. Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the bottom 8 data inputs, DB0-DB7, are used for data loading while the top 6 data inputs, DB8 to DB13, should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data are being loaded into the device. Byte Shift Input. When low, it shifts the data on DB0-DB7 into the DB8-DB13 half of the input register. Address inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is used to select all four DACs simultaneously. Load DAC Input (level sensitive). This input signal in conjunction with the WR and CS input signals, determines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the device's input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs simultaneously. Alternatively, if LDAC is brought low while new data is being entered, then the addressed DAC latch (and corresponding analog output) is updated immediately on the rising edge of WR.
BYSHF A0, A1, A2 LDAC
CLR
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are switched to the externally set potentials on the DSG pins (VOUT1 and VOUT2 follow DSGA while VOUT3 and VOUT4 follow DSGB). When CLR is brought high, the signal outputs remain at the DSG potentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored and the signal outputs remain switched to the potential on the DSG pins. Level-Triggered Write Input (active low). When active it is used in conjunction with CS to write data over the input data bus. Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, DAC outputs VOUT1 and VOUT2 are forced to the potential on the DSGA pin. Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, DAC outputs VOUT3 and VOUT4 are forced to the potential on the DSGB pin.
WR DSGA DSGB
-6-
REV. A
AD7834/AD7835
PIN CONFIGURATIONS PQFP
VREF (+)B VREF(-)B VREF(+)A VREF(+)A VREF(-)A VREF(-)A AGND
PLCC
VREF(+)B AGND VREF(-)B
VDD
VDD
VSS
VSS
NC
NC
NC
NC
NC
NC
44 43 42 41 40 39 38 37 36 35 34 NC 1 DSGA 2 VOUT1 3 VOUT 2 4 NC 5 A2 6 A1 7 A0 8 CLR 9 LDAC 10 BYSHF 11 12 13 14 15 16 17 18 19 20 21 22
PIN 1 IDENTIFIER
6 33 NC 32 DSGB 31 VOUT3 30 VOUT4 NC 7 DSGA 8 VOUT1 9 VOUT2 10 NC 11 A2 12 A1 13 A0 14 CLR 15 LDAC 16 BYSHF 17
5
4
NC
3
2
1
44 43 42 41 40
PIN 1 IDENTIFIER
NC
39 NC 38 DSGB 37 VOUT3 36 VOUT4 35 DB13 34 DB12 33 DB11 32 DB10 31 DB9 30 DB8 29 DB7
AD7835
TOP VIEW (Not to Scale)
29 DB13 28 DB12 27 DB11 26 DB10 25 DB9 24 DB8 23 DB7
AD7835
TOP VIEW (Not to Scale)
18 19 20 21 22 23 24 25 26 27 28
CS
DB1
DB3
DB5
WR
DB0
DB2
DGND
DB4
DB6
DB1
DB3
DB0
DB2
DB4
VCC
WR
DB5
NC = NO CONNECT
NC = NO CONNECT
TERMINOLOGY Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
signal from one DACs reference input which appears at the output of the other DAC. It is expressed in dBs. The AD7834 has no specification for Channel-to-channel isolation because it has one reference for all DACs. Channel-tochannel isolation is specified for the AD7835.
DAC-to-DAC Crosstalk
Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
DC Crosstalk
DAC-to-DAC Crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog O/P change at another converter. It is specified in nV-s.
Digital Crosstalk
Although the common input reference voltage signals are internally buffered, small IR drops in the individual DAC reference inputs across the die can mean that an update to one channel can produce a dc output change in one or other of the channel outputs. The four DAC outputs are buffered by op amps that share common VDD and VSS power supplies. If the dc load current changes in one channel (due to an update), this can result in a further dc change in one or other channel outputs. This effect is most obvious at high load currents and reduces as the load currents are reduced. With high impedance loads the effect is virtually unmeasurable.
Output Voltage Settling Time
The glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the Digital Crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by package lead resistance.
Full-Scale Error
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be VREF(+) - 1 LSB. FullScale Error does not include Zero-Scale Error.
Zero-Scale Error
This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV-secs. It is measured with the reference inputs connected to 0 V and the digital inputs toggled between all 1s and all 0s.
Channel-to-Channel Isolation
Zero-Scale Error is the error in the DAC output voltage when all 0s are loaded into the DAC latch. Ideally the output voltage, with all 0s in the DAC latch should be equal to VREF(-). ZeroScale Error is mainly due to offsets in the output amplifier.
Gain Error
Channel-to-channel isolation refers to the proportion of input
Gain Error is defined as (Full-Scale Error) - (Zero-Scale Error).
REV. A
-7-
DGND
DB6
CS
VCC
AD7834/AD7835-Typical Performance Characteristics
1.0 0.8 0.6 0.4
INL - LSBs
INL - LSBs
0.5 0.4 0.3 0.2 INL - LSBs 16 0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 2 4 6 8 10 CODE/1000 12 14 16 -0.5 0 2 4 6 8 10 CODE/1000 12 14
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 VREF(+) - Volts 6 7 8
0.2 0.0
-0.2 -0.4 -0.6 -0.8 -1.0
Figure 3. Typical INL Plot
Figure 4. Typical DNL Plot
Figure 5. Typical INL vs. VREF(+) (VREF(-) = -6 V)
1.0 0.8 0.6
0.5 0.45 DAC 1 0.4 0.35
INL - LSBs
0.8 0.7 0.6 DAC 1 DAC 4 0.4 0.3 0.2 ALL DACs FROM ONE DEVICE 0.1 0 -40 +25 TEMPERATURE - C +85 DAC 2
DAC 3
0.4
INL - LSBs
0.3 0.25 0.2 0.15 0.1 0.05 0 0 DAC 2
DAC 4
INL - LSBs
0.5
DAC 3
0.2 0.0
-0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 6 8 10 CODE/1000 12 14 16
TEMP = +25C ALL DACs FROM 1 DEVICE
2.5 5 VREF(+) - Volts
8
Figure 6. Typical INL vs. VREF(+) (VREF(+) - VREF(-) = 5 V)
Figure 7. Typical INL vs. Temperature
Figure 8. Typical DAC-to-DAC Matching
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
VOLTS
8
7.25 VERT = 2V/DIV HORIZ = 1.2s/DIV
8 VERT = 10mV/DIV HORIZ = 1s/DIV
-2.985
VERT = 100mV/DIV HORIZ = 1s/DIV
6
7.225
6
-3.005
4 VREF(+) = +7V VREF(-) = -3V
7.2 VOLTS
VOLTS
4 VREF(+) = +7V VREF(-) = -3V
-3.025 -3.045
VOLTS
2
7.175
2
0
7.15
0
-3.065
-2
-0.1 -0.2
-4
VERT = 25mV/DIV HORIZ = 2.5s/DIV
7.125
-2 VERT = 2V/DIV HORIZ = 1s/DIV -4
-3.085 -3.105
7.1
Figure 9. Typical Digital/Analog Glitch Impulse
Figure 10. Settling Time (+)
Figure 11. Settling Time (-)
-8-
REV. A
AD7834/AD7835
GENERAL DESCRIPTION DAC Architecture--General Table I. D23 Control D23 Control Function
Each channel consists of a segmented 14-bit R-2R voltage-mode DAC. The full- scale output voltage range is equal to the entire reference span of VREF(+) - VREF(-). The DAC coding is straight binary; all 0s produces an output of VREF(-); all 1s produces an output of VREF(+) - 1 LSB. The analog output voltage of each DAC channel reflects the contents of its own DAC latch. Data is transferred from the external bus to the input register of each DAC latch on a per channel basis. The AD7835 has a feature whereby using the A2 pin, data can be transferred from the input data bus to all four input registers simultaneously. Bringing the CLR line low switches all the signal outputs, VOUT1 to VOUT4, to the voltage level on the DSG pin. The signal outputs are held at this level after the removal of the CLR signal and will not switch back to the DAC outputs until the LDAC signal is exercised.
Data Loading--AD7834, Serial Input Device
0 1
Ignore following 23 bits of information. Use following 23 bits of address and data as normal.
D22 and D21: Decoded to select one of the four DAC channels within a device. The truth table for D22 and D21 is as shown below in Table II.
Table II. D22, D21 Control D22 D21 Control Function
0 0 1 1
0 1 0 1
Select Channel 1 Select Channel 2 Select Channel 3 Select Channel 4
A write operation transfers 24 bits of data to the AD7834. The first 8 bits are control data and the remaining 16 bits are DAC data (see Figure 12). The control data identifies the DAC channel to be updated with new data and which of 32 possible packages the DAC resides in. In any communication with the device the first 8 bits must always be control data. Note that the DAC output voltages, VOUT1 to VOUT4, can be updated to reflect new data in the DAC input registers in one of two ways. The first method normally keeps LDAC high and only pulses LDAC low momentarily to update all DAC latches simultaneously with the contents of their respective input registers. The second method ties LDAC low, and channel updating occurs on a per channel basis after new data has been clocked into the AD7834. With LDAC low, the rising edge of FSYNC transfers the new data directly into the DAC latch, updating the analog output voltage. Data being shifted into the AD7834 enters a 24-bit long shift register. If more than 24 bits are clocked in before FSYNC goes high, the last 24 bits transmitted are used as the control data and DAC data. Individual bit functions are discussed below. D23: Determines whether the following 23-bits of address and data should be used or should be ignored. This is effectively a software Chip Select bit. D23 is the first bit to be transmitted in the 24-bit long word.
D20-D16: Determines the package address. The five address bits allow up to 32 separate packages to be individually decoded. Successful decoding is accomplished when these five bits match up with the five hardwired pins on the physical package. D15-D0: DAC Data to be loaded into identified DAC Input Register. This data must have two leading 0s followed by 14 bits of data, MSB first. The MSB is in location D13 of the 24-bit data stream.
Data Loading--AD7835, Parallel Loading Device
Data can be loaded into the AD7835 in either straight 14-bit wide words or in two 8-bit bytes. In systems which can transfer 14-bit wide data, the BYSHF input should be hardwired to VCC. This sets up the AD7835 as a straight 14-bit parallel-loading DAC. In 8-bit bus systems where it is required to transfer data in two bytes, it is necessary to have the BYSHF input under logic control. In such a system the top 6 pins of the device data bus, DB8-DB13, must be hardwired to DGND. New low byte data is loaded into the lower 8 places of the selected input register by carrying out a write operation while holding BYSHF high. A second write operation is subsequently executed with BYSHF low and the 6 MSBs on the DB0-DB5 inputs (DB5 = MSB).
NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD. D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BIT TO USE/IGNORE FOLLOWING 23 BITS OF INFORMATION CHANNEL ADDRESS MSB, D1 CHANNEL ADDRESS LSB, D2 PACKAGE ADDRESS MSB, PA4 PACKAGE ADDRESS, PA3 PACKAGE ADDRESS, PA2 PACKAGE ADDRESS, PA1 PACKAGE ADDRESS LSB, PA0 DB8 DB9 DB10 THIRD MSB, DB11 SECOND MSB, DB12 MSB, DB13 SECOND LEADING ZERO FIRST LEADING ZERO DB6 DB7 DB4 DB5 DB3
LSB, DB0 SECOND LSB, DB1 THIRD LSB, DB2
Figure 12. Bit Assignments for 24-Bit Data Stream of AD7834
REV. A
-9-
AD7834/AD7835
When 14-bit transfers are being used, the DAC output voltages, VOUT1-VOUT4, can be updated to reflect new data in the DAC input registers in one of two ways. The first method normally keeps LDAC high and only pulses LDAC low momentarily to update all DAC latches simultaneously with the contents of their respective input registers. The second method ties LDAC low and channel updating occurs on a per channel basis after new data is loaded to an input register. In order to avoid the DAC output going to an intermediate value during a 2-byte transfer, LDAC should not be tied low permanently, but should be held high until the 2 bytes are written to the input register. When the selected input register has been loaded with the 2 bytes, LDAC should then be pulsed low to update the DAC latch and, hence, perform the digital-toanalog conversion. In many applications, it may be acceptable to allow the DAC output to go to an intermediate value during a 2-byte transfer. In such applications, LDAC can be tied low, thus using one less control line. The actual DAC input register that is being written to is determined by the logic levels present on the devices address lines, as shown in Table III.
Table III. AD7835--Address Line Truth Table A2 A1 A0 DAC Selected
C1 1F 7 9
Table IV. Code Table for Unipolar Operation Binary Number in DAC Latch MSB LSB Analog Output (VOUT)
11 10 01 00 00
1111 0000 1111 0000 0000
1111 0000 1111 0000 0000
1111 0000 1111 0001 0000
VREF (16383/16384) V VREF (8192/16384) V VREF (8191/16384) V VREF (1/16384) V 0V
NOTE VREF = VREF(+); VREF(-) = 0 V for unipolar operation. For VREF(+) = +5 V, 1 LSB = +5 V/2 14 = +5 V/16384 = 305 V.
Figure 14 shows the AD7834/AD7835 set up for 5 V operation. The AD588 provides precision 5 V tracking outputs which are fed to the VREF(+) and VREF(-) inputs of the AD7834/ AD7835. The code table for bipolar operation of the AD7834/ AD7835 is shown in Table V.
+15V +5V
Bipolar Configuration
R1 39k 4 6 2 3 1 14 15 16 12 8 13 VDD VREF(+) VCC VOUT VOUT (-5 TO +5V)
AD588
0 0 0 0 1
0 0 1 1 X
0 1 0 1 X
DAC 1 DAC 2 DAC 3 DAC 4 All DACs Selected
R2 100k
5 10 11 R3 100k
AD7834/ AD7835*
VREF(-) VSS SIGNAL GND -15V AGND DGND
Unipolar Configuration
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13 shows the AD7834/AD7835 in the unipolar binary circuit configuration. The VREF(+) input of the DAC is driven by the AD586, a +5 V reference. VREF(-) is tied to ground. Table IV gives the code table for unipolar operation of the AD7834/AD7835.
+15V +5V
Figure 14. Bipolar 5 V Operation
Table V. Code Table for Bipolar Operation Binary Number in DAC Latch Analog Output MSB LSB (VOUT)
2 6 8 C1 1nF
VDD VREF(+) R1 10k
VCC VOUT VOUT (0 TO +5V)
AD586
4
5
AD7834/ AD7835*
AGND VREF(-) VSS DGND SIGNAL GND -15V
11 10 10 01 00 00
1111 0000 0000 1111 0000 0000
1111 0000 0000 1111 0000 0000
1111 0001 0000 1111 0001 0000
VREF(-) + VREF (16383/16384) V VREF(-) + VREF (8193/16384) V VREF(-) + VREF (8192/16384) V VREF(-) + VREF (8191/16384) V VREF(-) + VREF (1/16384) V VREF(-) V
SIGNAL GND
*ADDITIONAL PINS OMITTED FOR CLARITY
NOTE VREF = (VREF(+) - VREF(-)). For VREF(+) = +5 V, and V REF(-) = -5 V, 1 LSB = 10 V/2 14 = 10 V/16384 = 610 V.
Figure 13. Unipolar +5 V Operation
Offset and gain may be adjusted in Figure 13 as follows: To adjust offset, disconnect the VREF(-) input from 0 V, load the DAC with all 0s and adjust the VREF(-) voltage until VOUT = 0 V. For gain adjustment, the AD7834/AD7835 should be loaded with all 1s and R1 adjusted until VOUT = 5 V(16383/16384) = 4.999695. Many circuits will not require these offset and gain adjustments. In these circuits R1 can be omitted. Pin 5 of the AD586 may be left open circuit and Pin 2 (VREF(-)) of the AD7834/AD7835 tied to 0 V.
In Figure 14, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588 while R3 adjusts the offset of both the +5 V and -5 V outputs together with respect to ground. For bipolar-zero adjustment, the DAC is loaded with 1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale is adjusted by loading the DAC with all 1s and adjusting R2 until VOUT = 5(8191/8192) V = 4.99939 V. When bipolar-zero and full-scale adjustment are not needed, R2 and R3 can be omitted. Pin 12 on the AD588 should be connected to Pin 11 and Pin 5 should be left floating.
-10-
REV. A
AD7834/AD7835
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7834/AD7835 is shown in Figure 15. It is capable of driving a load of 10 k in parallel with 200 pF. G1 to G6 are transmission gates that are used to control the power on voltage present at VOUT. G1 and G2 are also used in conjunction with the CLR input to set VOUT to the user defined voltage present at the DSG pin.
G1 DAC G3 G4 G2 G5 R G6 VOUT
VOUT has been disconnected from the DSG pin by the opening of G5 but will track the voltage present at DSG via the unity gain buffer.
Power-On with LDAC Low, CLR High
DSG
In many applications of the AD7834/AD7835 LDAC will be kept continuously low, thus updating the DAC after each valid data transfer. If LDAC is low when power is applied, then G1 is closed and G2 is open, thus connecting the output of the DAC to the input of the output amplifier. G3 and G5 will be closed and G4 and G6 open, connecting the amplifier as a unity gain buffer, as before. VOUT is connected to DSG via G5 and R (a thin film resistance between DSG and VOUT) until VDD and VSS reach approximately 10 V. Then, the internal power-on circuitry opens G3 and G5 and closes G4 and G6. This is the situation shown in Figure 18. VOUT is now at the same voltage as the DAC output.
G1 DAC G3 G4 G2 G5 R G6 VOUT
Figure 15. Block Diagram of AD7834/AD7835 Output Stage
Power-On with CLR Low, LDAC High
The output stage of the AD7834/AD7835 has been designed to allow output stability during power-on. If CLR is kept low during power-on, then just after power is applied to the part, the situation is as depicted in Figure 16. G1, G4 and G6 are open while G2, G3 and G5 are closed.
G1 DAC G3 G4 G2 G5 R G6 VOUT
DSG
Figure 18. Output Stage with LDAC Low
Loading the DAC and Using the CLR Input
DSG
Figure 16. Output Stage with VDD < 10 V
When LDAC goes low, it closes G1 and opens G2 as in Figure 18. The voltage at VOUT now follows the voltage present at the output of the DAC. The output stage remains connected in this manner until a CLR signal is applied. Then the situation reverts to that shown in Figure 17. Once again VOUT remains at the same voltage as DSG until LDAC goes low. This reconnects the DAC output to the unity gain buffer.
DSG Voltage Range
VOUT is kept within a few hundred millivolts of DSG via G5 and R. R is a thin-film resistor between DSG and VOUT. The output amplifier is connected as a unity gain buffer via G3 and the DSG voltage is applied to the buffer input via G2. The amplifiers output is thus at the same voltage as the DSG pin. The output stage remains configured as in Figure 16 until the voltage at VDD and VSS reaches approximately 10 V. By now the output amplifier has enough headroom to handle signals at its input and has also had time to settle. The internal power-on circuitry opens G3 and G5 and closes G4 and G6. This situation is shown in Figure 17. Now the output amplifier is connected in unity gain mode via G4 and G6. The DSG voltage is still applied to the noninverting input via G2. This voltage appears at VOUT.
G1 DAC G3 G4 G2 G5 R G6 VOUT
During power-on, the VOUT pins of the AD7834/AD7835 are connected to the relevant DSG pins via G6 and the thin film resistor, R. The DSG potential must obey the max ratings at all times. Thus, the voltage at DSG must always be within the range VSS - 0.3 V, VDD + 0.3 V. However, in order that the voltages at the VOUT pins of the AD7834/AD7835 stay within 2 V of the relevant DSG potential during power-on, the voltage applied to DSG should also be kept within the range AGND - 2 V, AGND + 2 V. Once the AD7834/AD7835 has powered on and the on-chip amplifiers have settled, the situation is as shown as in Figure 17. Any voltage that is now applied to the DSG pin is buffered by the same amplifier that buffers the DAC output voltage in normal operation. Thus, for specified operation, the maximum voltage that can be applied to the DSG pin increases to the maximum allowable VREF(+) voltage, and the minimum voltage that can be applied to DSG is the minimum VREF(-) voltage. After the AD7834/AD7835 has fully powered on, the outputs can track any DSG voltage within this minimum/maximum range.
POWER-ON OF THE AD7834/AD7835
DSG
Figure 17. Output Stage with VDD > 10 V and CLR Low
Power should normally be applied to the AD7834/AD7835 in the following sequence: first VDD and VSS, then VCC, then VREF(+) and VREF(-).
REV. A
-11-
AD7834/AD7835
The VREF pins should never be allowed to float when power is applied to the part. (VREF(+) should never be allowed to go below VREF(-)-0.3 V. VREF(-) should never be allowed to go below VSS-0.3 V. VDD should never be allowed to go below VCC-0.3 V. In some systems it may be necessary to introduce one or more Schottky diodes between pins to prevent the above situations arising at power-on. These diodes are shown in Figure 19. However in most systems, with careful consideration given to power supply sequencing, the above rules will be adhered to and protection diodes won't be necessary.
VREF(+)
the AD7834 while the MOSI output drives the serial data line, DIN, of the AD7834. The FSYNC signal is derived from port line PC7 in this example. For correct operation of this interface, the 68HC11 should be configured such that its CPOL bit is a 0 and its CPHA bit is a 1. When data is to be transferred to the part, PC7 is taken low. When the 68HC11 is configured like this, data on MOSI is valid on the falling edge of SCK. The 68HC11 transmits its serial data in 8-bit bytes, MSB first. The AD7834 expects the MSB of the 24-bit write first also. Eight falling clock edges occur in the transmit cycle. To load data to the AD7834, PC7 is left low after the first eight bits are transferred. A second byte of data is then transmitted serially to the AD7834. Then a third byte is transmitted, and when this transfer is complete, the PC7 line is taken high.
68HC11*
PC5 PC6
AD7834*
VREF(-)
SD103C 1N5711 1N5712
AD7834*
CLR LDAC FSYNC SCLK DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Power-ON Protection
MICROPROCESSOR INTERFACING AD7834 to 80C51 Interface
PC7 SCK MOSI
A serial interface between the AD7834 and the 80C51 microcontroller is shown in Figure 20. TXD of the 80C51 drives SCLK of the AD7834 while RXD drives the serial data line of the part. The 80C51 provides the LSB of its SBUF register as the first bit in the serial data stream. The AD7834 expects the MSB of the 24-bit write first. Therefore, the user will have to ensure that the data in the SBUF register is arranged correctly so that this is taken into account. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 80C51 transmits its data in 8-bit bytes with only 8 falling clock edges occurring in the transmit cycle. To load data to the AD7834, P3.3 is left low after the first eight bits are transferred. A second byte is then transferred, with P3.3 still kept low. After the third byte has been transferred, the P3.3 line is taken high.
80C51*
P3.5 P3.4 P3.3 TXD RXD
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7834 to 68HC11 Interface
In Figure 21, LDAC and CLR are controlled by the PC6 and PC5 port outputs. As with the 80C51, each DAC of the AD7834 can be updated after each three-byte transfer, or else all DACs can be simultaneously updated after twelve bytes have been transferred.
AD7834 to ADSP-2101 Interface
AD7834*
CLR LDAC FSYNC
An interface between the AD7834 and the ADSP-2101 is shown in Figure 22. In the interface shown, SPORT0 is used to transfer data to the part. SPORT1 is configured for alternate functions. FO, the flag output on SPORT1, is connected to LDAC and is used to load the DAC latches. In this way data can be transferred from the ADSP-2101 to all the input registers in the DAC and the DAC latches can be updated simultaneously. In the application shown, the CLR pin on the AD7834 is controlled by circuitry that monitors the power in the system.
POWER MONITOR
ADSP-2101*
SCLK DIN
AD7834*
CLR
FO
LDAC FSYNC SCLK DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS SCK
Figure 20. AD7834 to 80C51 Interface
DT
LDAC and CLR on the AD7834 are also controlled by 80C51 port outputs. The user can bring LDAC low after every three bytes have been transmitted to update the DAC which has been programmed. Alternatively, it is possible to wait until all the input registers have been loaded (twelve byte transmits) and then update the DAC outputs.
AD7834 to 68HC11 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7834 to ADSP-2101 Interface
Figure 21 shows a serial interface between the AD7834 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
The AD7834 requires 24 bits of serial data framed by a single FSYNC pulse. It is necessary that this FSYNC pulse stays low until all the data has been transferred. This can be provided by the ADSP-2101 in one of two ways. Both require setting the se-
-12-
REV. A
AD7834/AD7835
rial word length of the SPORT to 12 bits, with the following conditions: Internal SCLK; Alternate framing mode; Active low framing signal. Data can be transferred using the Autobuffering feature of the ADSP-2101, sending two 12-bit words directly after each other. This ensures a continuous TFS pulse. Alternatively, the first data word can be loaded to the serial port, the subsequent interrupt that is generated can be trapped and then the second data word can be sent immediately after the first. Again this produces a continuous TFS pulse that frames the 24 data bits.
AD7834 to DSP56000/DSP56001 Interface Interfacing the AD7835--16-Bit Interface
Figure 23 shows a serial interface between the AD7834 and the DSP56000/DSP56001. The serial port is configured for a word length of 24 bits, gated clock and with FSL0 and FSL1 control bits each set to "0." Normal Mode Synchronous operation is selected which allows the use of SC0 and SC1 as outputs controlling CLR and LDAC. The framing signal on SC2 has to be inverted before being applied to FSYNC. SCK is internally generated on the DSP56000/DSP56001 and is applied to SCLK on the AD7834. Data from the DSP56000/DSP56001 is valid on the falling edge of SCK.
DSP56000/ DSP56001*
SC0 SC1 SC2 SCK STD
The AD7835 can be interfaced to a variety of microcontrollers or DSP processors, both 8-bit and 16-bit. Figure 25 shows the AD7835 interfaced to a generic 16-bit microcontroller/DSP processor. BYSHF is tied to VCC in this interface. The lower address lines from the processor are connected to A0, A1 and A2 on the AD7835 as shown. The upper address lines are decoded to provide a chip select signal for the AD7835. They are also decoded (in conjunction with the lower address lines if need be) to provide a LDAC signal. Alternatively, LDAC could be driven by an external timing circuit or just tied low. The data lines of the processor are connected to the data lines of the AD7835. The selection of the DACs is as given in Table III.
CONTROLLER/ DSP PROCESSOR*
D13 DATA BUS D0 UPPER BITS OF ADDRESS BUS ADDRESS DECODE D0 CS LDAC A2 A1 A0 WR VCC
AD7835*
BYSHF D13
AD7834*
CLR LDAC FSYNC SCLK DIN
A2 A1 A0 R/W
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. AD7835 16-Bit Interface
8-Bit Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. AD7834 to DSP5600/DSP56001 Interface
AD7834 to TMS32020/TMS320C25
A serial interface between the AD7834 and the TMS32020/ TMS320C25 DSP processor is shown in Figure 24. The CLKX and FSX signals for the TMS32020/TMS32025 should be generated using an external clock/timer circuit. The CLKX and FSX pin should be configured as inputs. The TMS32020/ TMS320C25 should be set up for an 8-bit serial data length. Data can then be written to the AD7834 by writing three bytes to the serial port of the TMS32020/TMS320C25. In the configuration shown in Figure 24 the CLR input on the AD7834 is controlled by the XF output on the TMS32020/TMS320C25. The clock/timer circuit controls the LDAC input on the AD7834. Alternatively, LDAC could also be tied to ground to allow automatic update of the DAC latches after each transfer.
CLOCK/ TIMER
Figure 26 shows an 8-bit interface between the AD7835 and a generic 8-bit microcontroller/DSP processor. Pins D13 to D8 of the AD7835 are tied to DGND. Pins D7 to D0 of the processor are connected to pins D7 to D0 of the AD7835. BYSHF is driven by the A0 line of the processor. This maps the DAC upper bits and lower bits into adjacent bytes in the processors address space. Table VI shows the truth table for addressing the DACs in the AD7835. If, for example, the base address for the DACs in the processor address space is decoded by the upper address bits to location HC000, then the first DAC's upper and lower bits are at locations HC000 and HC001 respectively.
D13
CONTROLLER/ DSP PROCESSOR*
D7 DATA BUS D0
D8 DGND D7
AD7835*
D0 ADDRESS DECODE CS LDAC A2 A1 A0 BYSHF WR
TMS32020/ TMS320C25*
XF FSX CLKX DX
AD7834*
LDAC CLR FSYNC SCLK DIN
UPPER BITS OF ADDRESS BUS
A3 A2 A1 A0 R/W
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. AD7835 8-Bit Interface
Figure 24. AD7834 to TMS32020/TMS320C25 Interface
REV. A
-13-
AD7834/AD7835
When writing to the DACs, the lower 8 bits must be written first, followed by the upper 6 bits. The upper 6 bits should be output on data lines D0 to D5. Once again, the upper address lines of the processor are decoded to provide a CS signal. They are also decoded in conjunction with lines A3 to A0 to provide a LDAC signal. Alternatively, LDAC can be driven by an external timing circuit or, if it's acceptable to allow the DAC output to go to an intermediate value between 8-bit writes, LDAC can be tied low.
Table VI. DAC Selection, 8-Bit Interface Processor Address Lines A3 A2 A1 A0 DAC Selected
unique address by hardwiring each of the Package Address pins to VCC or DGND. Normal operation of the device occurs when PAEN is low. When serial data is being written to the AD7834s, only the device with the same package address as the package address contained in the serial data will accept data into the input registers. If, on the other hand, PAEN is high, the package address is ignored and the data is loaded into the same channel on each package. The main limitation with multiple packages is the output update rate. For example, if an output update rate of 10 kHz is required, then there are 100 s to load all DACs. Assuming a serial clock frequency of 10 MHz, it takes 2.5 s to load data to one DAC. Thus forty DACs or ten packages can be updated in this time. As the update rate requirement decreases, the number of possible packages increases.
Opto-Isolated Interface
1 1 0 0 0 0 0 0 0 0
X X 0 0 0 0 1 1 1 1
X X 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1
Upper 6 Bits of All DACs Lower 8 Bits of All DACs Upper 6 Bits, DAC 1 Lower 8 Bits, DAC 1 Upper 6 Bits, DAC 2 Lower 8 Bits, DAC 2 Upper 6 Bits, DAC 3 Lower 8 Bits, DAC 3 Upper 6 Bits, DAC 4 Lower 8-Bits, DAC 4
APPLICATIONS Serial Interface to Multiple AD7834s
Figure 27 shows how the Package Address pins of the AD7834 are used to address multiple AD7834s. The figure shows only 10 devices, but up to 32 AD7834s can each be assigned a
CONTROLLER
CONTROL OUT CONTROL OUT SYNC OUT SERIAL CLOCK OUT SERIAL DATA OUT
In many process control applications it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD7834 makes it ideal for opto-isolated interfaces as the number of interface lines is kept to a minimum. Figure 28 shows a 5-channel isolated interface to the AD7834. Multiple devices are connected to the outputs of the opto-coupler and controlled as explained above. To reduce the number of opto-isolators, the PAEN line doesn't need to be controlled if it is not used. If the PAEN line is not controlled by the microcontroller then it should be tied low at each device. If simultaneous updating of the DACs is not required, then LDAC pin on each part can be tied permanently low and a further opto-isolator is not needed.
VCC
CONTROLLER
AD7834* DEVICE 0
PAEN LDAC FSYNC SCLK DIN PA0 PA1 PA2 PA3 PA4
CONTROL OUT CONTROL OUT SYNC OUT SERIAL CLOCK OUT SERIAL DATA OUT
VCC
TO PAENs TO LDACs TO FSYNCs TO SCLKs TO DINs
AD7834* DEVICE 1
PAEN LDAC FSYNC SCLK DIN PA0 PA1 PA2 PA3 PA4
OPTO-COUPLER
Figure 28. Opto-Isolated Interface
Automated Test Equipment
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7834* DEVICE 9
PAEN LDAC FSYNC SCLK DIN PA0 PA1 PA2 PA3 PA4
VCC
The AD7834/AD7835 is particularly suited for use in an automated test environment. Figure 29 shows the AD7835 providing the necessary voltages for the pin driver and the window comparator in a typical ATE pin electronics configuration. Two AD588s are used to provide reference voltages for the AD7835. In the configuration shown, the AD588s are configured so that the voltage at Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the voltage at Pin 9. One of the AD588s is used as a reference for DACs 1 and 2. These DACs are used to provide high and low levels for the pin driver. The pin driver may have an associated offset. This can be nulled by applying an offset voltage to Pin 9 of the AD588. First, the code 1000 . . . 0000 is loaded into the DAC1 latch and the pin driver output is set to the DAC1 output. The
Figure 27. Serial Interface to Multiple AD7834s
-14-
REV. A
AD7834/AD7835
VOFFSET voltage is adjusted until 0 V appears between the pin driver output and DUT GND. This causes both VREF(+)A and VREF(-)A to be offset with respect to AGND by an amount equal to VOFFSET. However the output of the pin driver will vary from -5 V to +5 V with respect to DUT GND as the DAC input code varies from 000 . . . 000 to 111 . . . 111. The VOFFSET voltage is also applied to the DSG A pin. When a clear is performed on the AD7835, the output of the pin driver will be 0 V with respect to DUT GND.
+15V -15V 2 4 6 8 13 7 1F 10 11 12 +15V -15V 2 4 6 8 13 10 11 12 1F 16 3 1 15 VOUT3 VREF(+)B VREF(-)B AGND DUT GND 16 3 1 +15V VREF(+)A VREF(-)A VOUT2 DSG A 0.1F -15V VOUT1 PIN DRIVER VOFFSET
AD588
15 14 9
AD7834/AD7835 is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined at one place. If the AD7834/AD7835 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7834/AD7835. If the AD7834/AD7835 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7834/ AD7835. Digital lines running under the device should be avoided as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7834/AD7835 to avoid noise coupling. The power supply lines of the AD7834/ AD7835 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. The AD7834/AD7835 should have ample supply bypassing located as close to the package as possible, ideally right up against the device. Figure 30 shows the recommended capacitor values of 10 F in parallel with 0.1 F on each of the supplies. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
VCC 10F DGND 0.1F VDD 0.1F 10F AGND
AD7835*
DSG B DUT GND VDUT
VOUT4
AD588
14
7
8 DUT GND
WINDOW COMPARATOR TO TESTER
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. ATE Application
The other AD588 is used to provide a reference voltage for DACs 3 and 4. These provide the reference voltages for the window comparator shown in the diagram. Note that Pin 9 of this AD588 is connected to DUT GND. This causes VREF(+)B and VREF(-)B to be referenced to DUT GND. As DAC 3 and DAC 4 input codes vary from 000 . . . 000 to 111 . . . 111, VOUT3 and VOUT4 vary from -5 V to +5 V with respect to DUT GND. DUT GND is also connected to DSG B. When the AD7835 is cleared, VOUT3 and VOUT4 are cleared to 0 V with respect to DUT GND. Care must be taken to ensure that the maximum and minimum voltage specs for the AD7835 reference voltages are not broken in the above configuration.
Power Supply Bypassing and Grounding
AD7834/ AD7835*
VSS
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the
0.1F
10F
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. Power Supply Decoupling
REV. A
-15-
AD7834/AD7835
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Leaded Plastic DIP (N-28)
1.565 (39.70) 1.380 (35.10)
28 15
28-Leaded Cerdip (Q-28)
0.005 (0.13) MIN
28
0.100 (2.54) MAX
15
0.580 (14.73) 0.485 (12.32)
1 14
0.610 (15.49) 0.500 (12.70)
1 14
PIN 1 0.250 (6.35) MAX 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356)
0.060 (1.52) 0.015 (0.38)
0.625 (15.87) 0.600 (15.24)
0.195 (4.95) 0.125 (3.18)
PIN 1 1.490 (37.85) MAX 0.225 0.015 (0.38) MIN 0.150 (3.81) MIN 0.070 (1.78) SEATING 0.030 (0.76) PLANE 15 0
0.620 (15.75) 0.590 (14.99)
0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) MAX SEATING PLANE
(5.72) MAX
0.015 (0.381) 0.008 (0.204)
0.018 (0.46) 0.008 (0.20)
0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.125 (3.18) 0.014 (0.36) 0.090 (2.29)
28-Leaded SOIC (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
44-Pin PQFP (S-44)
0.548 (13.925) 0.546 (13.875) 0.096 (2.44) MAX 0.398 (10.11) 0.390 (9.91) 8 0.8
34 33 23 22
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.037 (0.94) 0.025 (0.64) SEATING PLANE
1
14
TOP VIEW
PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45 0.0098 (0.25)
(PINS DOWN)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
SEATING 0.0125 (0.32) PLANE 0.0091 (0.23)
8 0
0.0500 (1.27) 0.0157 (0.40)
44
12 1 11
0.040 (1.02) 0.032 (0.81)
0.040 (1.02) 0.032 (0.81)
0.083 (2.11) 0.077 (1.96)
0.016 (0.41) 0.012 (0.30)
0.033 (0.84) 0.029 (0.74)
44-Pin PLCC (P-44A)
0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
6 7 PIN 1 IDENTIFIER
40 39
0.050 (1.27) BSC
0.63 (16.00) 0.59 (14.99)
TOP VIEW
(PINS DOWN)
0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
17 18
29 28
0.020 (0.50) R
0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40)
-16-
REV. A
PRINTED IN U.S.A.
0.056 (1.42) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38)
C2027a-6-9/95

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